This invention relates to integrated circuits and more particularly to output buffer stages and the fall time of such output stages when the output voltage switches from a high to a low voltage.
FIG. 1 is a diagram depicting a typical integrated circuit package 100 including an integrated circuit which has a plurality of output buffers 103-1 through 103-N. The ground lead of output buffers 103-1 through 103-N are connected to external ground 102 via a lead of package 100 which has associated therewith inductance 101. Each output buffer 103-1 through 103-N is connected to an associated load 112-1 through 112-N, respectively. When current is sunk from one or more loads 112-1 through 112-N, that current flows to ground 102 through inductance 101. If all output buffers 103-1 through 103-N are sinking a load current I.sub.load from loads 112-1 through 112-N, inductance 101 carriers a current N(I.sub.load).
As is well known, inductance 101 causes ground bounce, i.e., an increase in the effective ground voltage above ground 102, when there is a change in the amount of current flowing through inductor 101. If for example output buffer 103-1 is sinking current from load 112-1 in a steady state condition, load 112-1 is held to a voltage substantially equal to the voltage of ground 102. If then one or more of the other output buffers switches in order to sink additional current through inductor 101, the "ground" voltage applied to load 112-1 will rise in voltage during the transient increase in current through inductor 101.
FIG. 2 is a schematic diagram of a typical prior art medium speed output buffer. An input signal is applied to node N21 in order to control output pull up transistor 233 and output pull down transistor 235 which in turn source and sink, respectively, current to load 212. With a logical one input signal applied to node N21, transistor 222 turns on, causing diode 224 to reverse bias, causing pull up resistor 225 to supply base drive to transistor 226. Transistor 226 thus turns on, thereby turning off transistor 229, and in turn turning on phase splitter transistor 232. With phase splitter transistor 232 turned on, pull up transistor 233 is turned off and pull down transistor is turned on, sinking current I.sub.load from load 212 through inductor 201 to ground 202. This causes the voltage applied to load 212 to switch from a high to a low voltage, as shown in FIG. 4. The delay between the time a high signal is applied to node N21 and the output voltage applied to load 212 goes low is caused by two mechanisms, the propagation delay through the circuitry between node N21 and output transistors 233 and 235, and the fall time caused by the presence of package inductance 201 which prevents the voltage applied to load 212 from falling to ground instantaneously.
Of importance, medium speed circuit 200 includes node N21 having a relatively large time constant, since capacitor 220 and pull up resistor 221 are relatively large. Circuit 200 also includes node N22 at the base of phase splitter transistor 232, which has a relatively small time constant, due to the rather small parasitic capacitance on node N22.
FIG. 3 is a circuit diagram of a typical prior art high speed output buffer. High speed output buffer 300 is similar to the medium speed output buffer 200 of FIG. 2 except that the inversions provided by transistors 226 and 229 of FIG. 2 are eliminated. This results in node N32 having a relatively large effective time constant, since node N32 follows node N31 through transistor 332 and diode 324. This has the effect of slowing the high to low transition of the output signal applied to load 312, while providing a low propagation delay.
Unfortunately, as current through inductor 301 changes, inductor 301 acts as a feedback impedance to the common emitter amplifier formed by transistors 332 and 335. Since node N32 has a large RC time constant, the voltage on node N32 acts as a small signal to the common emitter amplifier. The effect of the feedback impedance provided by inductor 301 reduces circuit gain and thus the output edge rate.
FIG. 5 is a diagram depicting the waveforms associates with high speed output buffer circuit 300 of FIG. 3, showing a smaller propagation delay than that of FIG. 4, but with an increased percentage of the total delay due to inductance effects.
FIG. 6 depicts a prior art integrated circuit lead frame 60 including two separate ground leads 61 and 62 for separate connections of grounds on an integrated circuit placed within cavity 64 of lead frame 60, for ultimate connection at pin 63 to a circuit ground. Such package has been used in the past in order to minimize ground noise problems.
FIG. 7 is a schematic diagram depicting a model of a typical prior art output circuit.